More than 20 years experience in semiconductors, 18 years experience in MEMS industry, multi-substrate MEMS, Wafer-Level Packaging (knowledge in Fan-Out), MOEMS, photonics,  expert  in DRIE and plasma etching, wide knowledge in photolithography, wet etch,  striping, deposition,wafer-level bonding, etc. 

Integration solution for MEMS process microfabrication.

  • Build and design a robust MEMS process flow to reach your desired performances as early as possible.
  • MEMS Simulation and MEMS Design.
  • Find the right foundry to make your MEMS.
  • Evaluate risks using Design or Process Failure Mode and Effect Analysis (DFMEA and PFMEA).
  • Elaborate risk mitigation plan.
  • Assit your Fabless business model to bring your device in high volume production.
  • Expert in plasma etching, I can assist your development in plasma etching (DRIE or RIE).


  • Experience in developing complex multi-substrate MEMS/MOEMS processes (involving up to 6 wafer-level bondings).
  • Deeply involved in many MEMS projects, some involving in depth material science, some micro-mirrors, IR-imagers, some involving acoustics, inertial sensors, fluidic device, pressure sensors, etc. This includes many aspects such as process step development, material properties development, process tool modifications, handling tools modification development, and very low defect level optimization.
  • Experience in Wafer Level Packaging and knowledge in Fan-Out.
  • Extensive knowledge in photolithography, wet etch, TMAH,  striping, PECVD, Sputter deposition, wafer-level bonding, VHF, etc.
  • Experience in challenging etching development: Filled Through Silicon Via, TSV reveal, 2-level DRIE, dry etching of exotic materials, complex DRIE shapes, tight critical dimensions for inertial devices, etc.
  • Very familiar with SPC, 8D problem solving, cross-contamination, and everything that strict quality rules foundries want to hear about.

Also Offers training course on "Plasma Etching for Semiconductors" (1-day course)
Next course, please contact: